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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. document no. u14022ej1v0ds00 (1st edition) date published august 2000 ns cp(k) printed in japan 8-bit single-chip microcontroller data s heet mos integrated circuit m m m m pd78f9177 , 78f9177 y the mark shows major revised the m pd78f9177 and m pd78f9177y are m pd789177, 789177y subseries (small, general-purpose) in the 78k/0s series. the m pd78f9177 replaces the internal rom of the m pd789176 and m pd789177 with flash memory, while the m pd78f9177y replaces the rom of the m pd789176y and m pd789177y with flash memory. because flash memory allows the program to be written and erased electrically with the device mounted on the board, this product is ideal for the evolution stages of system development, small-scale production and rapid development of new products. detailed function descriptions are provided in the following users manuals. be sure to read them before designing. m pd789167, 789177, 789167y, 789177y subseries users manual: u14186e 78k/0s series user's manual instruction: u11047e features ? pin compatible with mask rom version (except v pp pin) ? flash memory: 24 kbytes ? high-speed ram: 512 bytes ? minimum instruction execution time can be changed from high-speed (0.4 m s: @5.0-mhz operation with main system clock) to ultra-low-speed (122 m s: @ 32.768-khz operation with subsystem clock) ? 10-bit resolution a/d converter: 8 channels ? i/o ports: 31 ? serial interface: 2 channels ? 3-wire serial i/o mode / uart mode: 1 channel ? smb ( m pd78f9177y only): 1 channel ? timers: 6 channels ? 16-bit timer: 1 channel ? 8-bit timer/event counter: 2 channels ? 8-bit timer: 1 channel ? watch timer: 1 channel ? watchdog timer: 1 channel ? on-chip 16-bit multiplier ? power supply voltage: v dd = 1.8 to 5.5 v ? 2000
2 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 applications power windows, battery management unit, side air bags, etc ordering information (1) m m m m pd78f9177 part number package m pd78f9177gb-8es 44-pin plastic qfp (10 10) (2) m m m m pd78f9177y part number package m pd78f9177ygb-8es 44-pin plastic lqfp (10 x 10) m pd78f9177yga-9eu 48-pin plastic tqfp (fine pitch) (7 x 7)
3 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 78k/0s series development the products in the 78k/0s series are listed below. the names enclosed in boxes are subseries names. 78k/0s series small, general-purpose small, general-purpose + a/d for inverter control for driving lcd for assp 44 pins 44 pins 42/44 pins 28 pins 44 pins 30 pins 30 pins 30 pins 30 pins 30 pins 30 pins 44 pins products under mass production products under development y subseries supports smb. pd789014 80 pins 80 pins 64 pins 64 pins 64 pins 64 pins 64 pins 64 pins 44 pins 44 pins 20 pins 20 pins m pd789026 m pd789046 pd789026 with subsystem clock added pd789014 with timer reinforced and rom and ram expanded uart. low-voltage (1.8-v) operation pd789167 with improved a/d pd789104a with improved timer pd789146 with improved a/d pd789104a with eeprom added pd789124a with improved a/d rc oscillation model of pd789104a pd789104a with improved a/d pd789026 with a/d and multiplier added pd789407a with improved a/d pd789456 with improved i/o pd789446 with improved a/d pd789426 with improved display output pd789426 with improved a/d pd789306 with a/d added rc oscillation model of pd789306 basic subseries for driving lcd for pc keyboard. internal usb function for key pad. internal poc rc oscillation model of pd789860 for keyless entry. internal poc and key return circuit internal inverter control circuit and uart m pd789104a m pd789114a m pd789842 m pd789124a m pd789134a m pd789146 m pd789156 m pd789167 m pd789177 m pd789306 m pd789316 m pd789426 m pd789436 m pd789860 m pd789861 m pd789840 m pd789800 m pd789446 m pd789456 m pd789167y m pd789177y m m m m m m m m m m m m m m m m m m m pd789407a m pd789417a m 88 pins segment: 40 pins, common: 16 pins pd789830 m 144 pins segment/common output: 96 pins pd789835 m for driving dot lcd 52 pins 52 pins for remote controller. internal lcd controller/driver pd789327 m pd789467 m pd789327 with a/d added m
4 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 the major differences between subseries are shown below. timer rom capacity 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o v dd min value remark m pd789046 16 k 1 ch m pd789026 4 k-16 k 1 ch 1 ch 34 pins small, general- purpose m pd789014 2 k-4 k 2 ch - - 1 ch -- 1 ch (uart:1 ch) 22 pins 1.8 v - m pd789177 - 8 ch m pd789167 16 k-24 k 3 ch 1 ch 8 ch - 31 pins - m pd789156 - 4 ch m pd789146 8 k-16 k 4 ch - internal eeprom m pd789134a 4 ch m pd789124a 4 ch - rc oscillation version m pd789114a - 4 ch small, general- purpose + a/d m pd789104a 2 k-8 k 1 ch 1 ch - 1 ch 4 ch - 1 ch (uart: 1 ch) 20 pins 1.8 v - for inverter control m pd789842 8 k-16 k 3 ch note 1 ch 1 ch 8 ch - 1 ch (uart: 1 ch) 30 pins 4.0 v - m pd789417a 7 ch m pd789407a 12 k-24 k 3 ch 7 ch - 43 pins m pd789456 - 6 ch m pd789446 6 ch - 30 pins m pd789436 - 6 ch m pd789426 12 k-16 k 6 ch 1 ch (uart: 1 ch) 40 pins - m pd789316 rc oscillation version for lcd driving m pd789306 8 k to 16k 2 ch 1 ch 1 ch 1 ch - - 2 ch (uart: 1 ch) 23 pins 1.8 v - m pd789835 24 k-60 k 6 ch - 3 ch 28 pins 1.8 v for dot lcd driving m pd789830 24 k 1 ch 1 ch 1 ch 1 ch - - 1 ch 30 pins 2.7 v - m pd789467 1 ch - 18 pins m pd789327 4 k-24 k 2 ch - 1 ch 1 ch - 1 ch 21 pins 1.8 v internal lcd m pd789800 - 2 ch (usb: 1 ch) 31 pins 4.0 v m pd789840 8 k 1 ch 4 ch 1 ch 29 pins 2.8 v - m pd789861 rc oscillation version, internal eeprom assp m pd789860 4 k 2 ch - - 1 ch - - - 14 pins 1.8 v internal eeprom note 10-bit timer: 1 channel function subseries name
5 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 overview of functions item m pd78f9177 m pd78f9177y flash memory 24 kbytes internal memory high-speed ram 512 bytes minimum instruction execution time ? 0.4/1.6 m s (@5.0-mhz operation with main system clock) ? 122 m s (@ 32.768-khz operation with sub system clock) general-purpose registers 8 bits 8 registers instruction set ? 16-bit operations ? bit manipulations (set, reset, test) multiplier 8 bits 8 bits = 16 bits i/o ports total: 31 ? cmos input: 8 ? cmos i/o: 17 ? n-ch open drain: 6 a/d converters 10-bit resolution 8 channels serial interfaces 3-wire serial i/o/uart : 1 channel 3-wire serial i/o / uart: 1 channel smb: 1 channel timers ? 16-bit timer:1 channel ? 8-bit timer/event counter:2 channels ? 8-bit timer:1 channel ? watch timer:1 channel ? watchdog timer:1 channel timer output 4 output buzzer output 1 internal: 10, external: 4 ( m pd78f9177) maskable internal: 12, external: 4 ( m pd78f9177y) vectored interrupt sources non-maskable internal: 1 power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = - 40c to + 85c package 44-pin plastic lqfp (10 10) 44-pin plastic lqfp (10 x10) 48-pin plastic tqfp (fine pitch) (7 x 7)
6 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 contents 1. pin configuration (top view) ................................................................................................. 7 2. block diagram................................................................................................................ ............. 10 3. pin functions................................................................................................................ ................ 11 3.1 port pins ................................................................................................................... ............................... 11 3.2 non-port pins............................................................................................................... ........................... 12 3.3 pin i/o circuits and recommended connection of unused pins ...................................................... 13 4. cpu architecture............................................................................................................. .......... 15 5. flash memory programming ................................................................................................ 16 5.1 selecting communication mode ............................................................................................... ........... 16 5.2 function of flash memory programming ............................................................................................ 17 5.3 flashpro iii connection example ............................................................................................ ............. 17 5.4 example of settings for flashpro iii (pg-fp3) .............................................................................. ...... 19 6. instruction set overview .................................................................................................... .. 20 6.1 conventions ............................................................................................................................... ............ 20 6.2 operations ................................................................................................................. ............................. 22 7. electrical specifications.................................................................................................... .. 27 8. characteristics curves ...................................................................................................... .. 45 9. package drawing ............................................................................................................. ......... 46 10. recommended soldering conditions ............................................................................... 48 appendix a. differences between m m m m pd78f9177, 78f9177y, and mask rom versions ...... 49 appendix b. development tools ............................................................................................... 50 appendix c. related documents ............................................................................................... 52
7 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 1. pin configuration (top view) ? 44-pin plastic lqfp (10 10) m pd78f9177gb-8es m pd78f9177ygb-8es p60/ani0 p61/ani1 p62/ani2 p63/ani3 p64/ani4 p65/ani5 p66/ani6 p67/ani7 av ss p10 p11 33 32 31 30 29 28 27 26 25 24 23 p01 p00 p26/to80 p25/ti80/ss20 v dd0 v ss0 x1 x2 reset xt1 xt2 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 av ref av dd p53 p52 p51 p50 p05 v ss1 p04 p03 p02 p30/intp0/ti81/cpt90 p31/intp1/to81 p32/intp2/to90 p33/intp3/to82/bzo90 p20/sck20/asck20 v dd1 p21/so20/t x d20 p22/si20/r x d20 p23/scl0 note p24/sda0 note v pp note the scl0 and sda0 pins are available in m pd78f9177y product only. cautions 1. connect the v pp pin directly to v ss0 or v ss1 . 2. connect the av dd pin to v dd0 . 3. connect the av ss pin to v ss0 .
8 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 ? 44-pin plastic qfp (fine pitch) (7 7) m pd78f9177yga-9eu p60/ani0 p61/ani1 p62/ani2 p63/ani3 p64/ani4 p65/ani5 p66/ani6 p67/ani7 av ss p10 p11 ic2 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 p01 p00 p26/to80 p25/tl80/ss20 v dd0 ic2 v ss0 x1 x2 reset xt1 xt2 p30/intp0/tl81/cpt90 p31/intp1/to81 p32/intp2/to90 p33/intp3/to82/bzo90 p20/sck20/asck20 v dd1 ic2 p21/so20/txd20 p22/sl20/rxd20 p23/scl0 p24/sda0 v pp av ref av dd p53 p52 ic0 p51 p50 p05 v ss1 p04 p03 p02 cautions 1. connect the v pp pin directly to the v ss0 or v ss1 pin in normal operation mode. 2. connect the ic0 (internally connected) pin directly to v ss0 or v ss1 . 3. leave the ic2 pin open. 4. connect the av dd pin to v dd0 . 5. connect the av ss pin to v ss0 .
9 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 ani0 to ani7: analog input reset: reset asck20: asynchronous serial input rxd20: receive data av dd : analog power supply sck20: serial clock (for sio20) av ref : analog reference voltage scl0 note2 : serial clock (for smb0) av ss : analog ground sda0 note2 : serial data bzo90: buzzer output si20: serial input cpt90: capture trigger input so20: serial output ic0 note1 ,ic2 note2 : internally connected ss20: chip select input intp0 to intp3: interrupt from peripherals ti80, ti81: timer input p00 to p05: port 0 to80 to to82, to90: timer output p10, p11: port 1 txd20: transmit data p20 to p26: port 2 v dd0 , v dd1 : power supply p30 to p33: port 3 v pp : programming power supply p50 to p53: port 5 v ss0 , v ss1 : ground p60 to p67: port 6 x1, x2: crystal (main system clock) xt1, xt2: crystal (subsystem clock) notes 1. the ic0 pin is available in 48-pin plastic tqfp (fine pitch) only. 2. the ic2, scl0, and sda0 pins are available in m pd78f9177y product only.
10 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 2. block diagram ram v dd0 v dd1 v ss0 v ss1 v pp ic0 ic2 note3 78k/0s cpu core rom ti80/ss20/p25 8-bit timer/ event counter80 p00-p05 port0 p10, p11 port1 p20-p26 port2 p30-p33 port3 p50-p53 port5 p60-p67 port6 system control 8-bit timer82 16-bit timer90 watch timer watchdog timer sio20 to80/p26 8-bit timer/ event counter81 ti81/intp0/cpt90/p30 to81/intp1/p31 cpt90/intp0/ti81/p30 to90/intp2/p32 bzo90/intp3/to82/p33 to82/intp3/bzo90/p33 sck20/asck20/p20 si20/r x d20/p22 so20/t x d20/p21 ss20/ti80/p25 multiplier ani0/p60- ani7/p67 av dd av ss av ref a/d converter reset x1 x2 xt1 xt2 interrupt control intp0/ti81/cpt90/p30 intp1/to81/p31 intp2/to90/p32 intp3/to82/bzo90/p33 smb note1 scl0/p23 sda0/p24 notes 1. smb is available in m pd78f9177y product only. 2. the ic0 pin is available in 48-pin plastic tqfp (fine pitch) only. 3. the ic2 pin is available in m pd78f9177y product only. note2
11 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 3. pin functions 3.1 port pins pin name i/o function after reset alternate function p00 to p05 i/o port 0 6-bit input/output port input/output mode can be specified in 1-bit units when used as an input port, an on-chip pull-up resistor can be specified by software. input - p10, p11 i/o port 1 2-bit input/output port input/output mode can be specified in 1-bit units when used as an input port, an on-chip pull-up resistor can be specified by software. input - p20 sck20/asck20 p21 so20/txd20 p22 si20/rxd20 p23 scl0 note p24 sda0 note p25 ti80/ss20 p26 i/o port 2 7-bit input/output port input/output mode can be specified in 1-bit units for p20 to p22, p25, and p26, an on-chip pull-up resistor can be specified by software. only p23 and p24 can be used as n-ch open-drain input/output port pins. input to80 p30 intp0/ti81/cpt90 p31 intp1/to81 p32 intp2/to90 p33 i/o port 3 4-bit input/output port input/output mode can be specified in 1-bit units on-chip pull-up resistor can be specified by software. input intp3/to82/bzo90 p50 to p53 i/o port 5 4-bit n-ch open-drain input/output port input/output mode can be specified in 1-bit units input - p60 to p67 input port 6 8-bit input-only port input ani0 to ani7 note m pd78f9177y only
12 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 3.2 non-port pins pin name i/o function after reset alternate function intp0 p30/ti81/cpt90 intp1 p31/to81 intp2 p32/to90 intp3 input external interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input p33/to82/bzo90 si20 input serial data input to serial interface input p22/rxd20 so20 output serial data output from serial interface input p21/txd20 sck20 i/o serial clock input/output for serial interface input p20/asck20 ss20 input chip select i nput to serial interface input p25/ti80 asck20 input serial clock input for asynchronous serial interface input p20/sck20 rxd20 input serial data input for asynchronous serial interface input p22/si20 txd20 output serial data output for asynchronous serial interface input p21/so20 scl0 note1 i/o smb0 clock input/output input p23 sda0 note1 i/o smb0 data input/output input p24 ti80 input external count clock input to 8-bit timer/event counter (tm80) input p25/ss20 ti81 input external count clock input to 8-bit timer/event counter (tm81) input p30/intp0/cpt90 to80 output 8-bit timer/event counter (tm80) output input p26 to81 output 8-bit timer/event counter (tm81) output input p31/intp1 to82 output 8-bit timer (tm82) output input p33/intp3/bzo90 to90 output 16-bit timer (tm90) output input p32/intp2 bzo90 output 16-bit timer (tm90) buzzer output input p33/intp3/to82 cpt90 input capture edge input input p30/intp0/ti81 ani0 to ani7 input a/d converter analog input input p60 to p67 av ref - a/d converter reference voltage -- av ss - a/d converter ground potential -- av dd - a/d converter analog power supply -- x1 input -- x2 - connecting crystal resonator for main system clock oscillation -- xt1 input -- xt2 - connecting crystal resonator for sub system clock oscillation -- v dd0 - positive power supply -- v dd1 - positive power supply (other than ports) -- v ss0 - ground potential -- v ss1 - ground potential (other than ports) -- reset input system reset input input - v pp - sets flash memory programming mode. applies high voltage when a program is written or verified. connect directly to v ss0 or v ss1 in normal operation mode. -- ic0 note2 - internally connected. connect this pin directly to the v ss0 or v ss1 pin. -- ic2 note1 - internally connected. leave this pin open. -- notes 1. m pd78f9177y only. 2. 48-pin plastic tqfp (fine pitch) only.
13 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 3.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins is shown in table 3-1. for the input/output circuit configuration of each type, refer to figure 3-1. table 3-1. type of i/o circuit for each pin and connection of unused pins pin name i/o circuit type i/o recommended connection of unused pins p00 to p05 p10, p11 5-h p20/sck20/asck20 p21/so20/txd20 p22/si20/rxd20 8-c input: independently connects to v dd0 , v dd1 or v ss0 , v ss1 via a resistor. output: leave open. p23/scl0 note1 p24/sda0 note1 13-x input: independently connects to v dd0 or v dd1 via a resistor. output: leave open. p25/ti80/ss20 p26/to80 input: independently connects to v dd0 , v dd1 or v ss0 , v ss1 via a resistor. output: leave open. p30/intp0/ti81/cpt90 p31/intp1/to81 p32/intp2/to90 p33/intp3/to82/bzo90 8-c input: independently connects to v ss0 or v ss1 via a resistor. output: leave open. p50 to p53 13-t i/o input: independently connects to v dd0 or v dd1 via a resistor. output: leave open. p60/ani0 to p67/ani7 9-c input connect directly to v dd0 , v dd1 or v ss0 , v ss1 . xt1 input connect to v ss0 or v ss1 . xt2 - - leave open. reset 2 input - v pp ic0 note2 connect directly to v ss0 or v ss1 . ic2 note1 -- leave open. notes 1. the ic2, scl0, and sda0 pins are available in m pd78f9177y product only. 2. 48-pin plastic tqfp (fine pitch) only.
14 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 figure 3-1. pin input/output circuits schmitt-triggered input with hysteresis characteristics type 2 in type 5-h pull-up enable data output disable input enable v dd0 p-ch v dd0 p-ch in/out n-ch type 13-t v ss0 v ss0 type 8-c pull-up enable data output disable v dd0 p-ch v dd0 p-ch in/out n-ch v ss0 type 9-c type 13-x output data output disable in/out n-ch input buffer with intermediate withstand voltage input enable v ss0 output data output disable in/out input buffer with 5-v withstand voltage comparator n-ch in comparator + - v ref (threshold voltage) av ss p-ch n-ch input enable
15 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 4. cpu architecture products in the m pd78f9177 and m pd78f9177y can access up to 64 kbytes of memory space. figure 4-1 shows the memory map. figure 4-1. memory map special function registers 256 8 bits internal high-speed ram 512 8 bits program memory space data memory space program area program area callt table area reserved vector table area internal flash memory 24576 x 8 bits ffffh ff00h feffh fd00h fcffh 5fffh 0080h 007fh 0040h 003fh 0024h 0023h 0000h 0000h 5fffh 6000h
16 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 5. flash memory programming the on-chip program memory in the m pd78f9177 and m pd78f9177y is flash memory. the flash memory can be written with the m pd78f9177 and m pd78f9177y mounted on the target system (on- board). connect the dedicated flash programmer (flashpro iii (part number: fl-pr3, pg-fp3)) to the host machine and target system to write the flash memory. remark fl-pr3 is made by naito densei machida mfg. co., ltd. 5.1 selecting communication mode the flash memory is written by using flashpro iii and by means of serial communication. select a communication mode from those listed in table 5-1. to select a communication mode, the format shown in figure 5-1 is used. each communication mode is selected by the number of v pp pulses shown in table 5-1. table 5-1. communication mode communication mode pins used number of v pp pulses 3-wire serial i/o sck20/asck20/p20 so20/txd20/p21 si20/rxd20/p22 0 smb note1 scl0/p23 sda0/p24 4 uart txd20/so20/p21 rxd20/si20/p22 8 pseudo 3-wire mode note2 p00 (serial clock input) p01 (serial data output) p02 (serial data input) 12 notes 1. m pd78f9177y only 2. serial transfer is performed by controlling a port by software. caution be sure to select a communication mode based on the v pp pulse number shown in table 5-1. figure 5-1. communication mode selection format 10 v v ss v dd v pp v dd v ss reset 12 n
17 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 5.2 function of flash memory programming by transmitting/receiving commands and data in the selected communication mode, operations such as writing to the flash memory are performed. table 5-2 shows the major functions of flash memory programming. table 5-2. functions of flash memory programming function description batch erase erases all contents of memory batch blank check checks erased state of entire memory data write write to flash memory based on write start address and number of data written (number of bytes) batch verify compares all contents of memory with input data 5.3 flashpro iii connection example how the flashpro iii is connected to the m pd78f9177 and m pd78f9177y differs depending on the communication mode (3-wired serial i/o, smb, uart, or pseudo 3-wire mode). figures 5-2 to 5-5 show the connection in the respective mode. figure 5-2. flashpro iii connection in 3-wired serial i/o mode v pp n note v dd reset sck so si gnd v pp v dd0 , v dd1 , av dd reset clk x1 sck20 si20 so20 v ss0 , v ss1 , a vss flashpro iii pd78f9177, 78f9177y m note n = 1, 2
18 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 figure 5-3. flashpro iii connection in smb mode v pp n note v dd reset so si gnd v pp v dd0 , v dd1 , av dd reset clk x1 scl0 sda0 v ss0 , v ss1 , av ss flashpro iii pd78f9177y m note n = 1, 2 figure 5-4. flashpro iii connection in uart mode v pp n note v dd reset so si gnd v pp v dd0 , v dd1 , av dd reset clk x1 rxd20 txd20 v ss0 , v ss1 , av ss flashpro iii pd78f9177, 78f9177y m note n = 1, 2 figure 5-5. flashpro iii connection in pseudo serial i/o mode (when port 0 is used) v pp n note v dd sck so si gnd reset v pp v dd0 , v dd1 , av dd reset clk x1 p00 (serial clock) p02 (serial input) p01 (serial output) v ss0 , v ss1 , av ss flashpro iii pd78f9177, 78f9177y m note n = 1, 2
19 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 5.4 example of settings for flashpro iii (pg-fp3) set as follows when writing to flash memory using the flashpro iii (pg-fp3). <1> download the parameter file. <2> select the serial mode and the serial clock using the type command. <3> the following is a setting example using the pg-fp3. table 5-3. example using pg-fp3 communication mode setting example using pg-fp3 number of v pp pulses note1 comm port sio ch-0 on target board cpu clk in flashpro on target board 4.1943 mhz sio clk 1.0 mhz in flashpro 4.0 mhz 3-wired serial i/o mode sio clk 1.0 mhz 0 comm port iic-ch0 slave address 10h iic clock 100 khz cpu clock in flashpro flashpro clock 4.0 mhz note3 smb note2 multiple rate 01.00 4 comm port uart-ch0 cpu clk on target board on target board 4.1943 mhz uart uart bps 9600 bps note4 8 comm port port a on target board cpu clk in flashpro on target board 4.1943 mhz sio clk 1.0 mhz in flashpro 4.0 mhz pseudo 3-wire mode sio clk 1.0 mhz 12 notes 1. the number of v pp pulses supplied from the flashpro iii during serial communication initialization. the pins to be used in communication are determined by this number of pulses. 2. m pd78f9177y only. 3. select one of 4.0 mhz or 3.125 mhz. 4. select one of 9600 bps, 19200 bps, 38400 bps, or 76800 bps. remark comm port : selection of serial port sio clk : selection of serial clock frequency cpu clk : selection of cpu clock source to be input
20 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 6. instruction set overview this section lists the m pd78f9177 and m pd78f9177y instruction set. 6.1 conventions 6.1.1 operand identifiers and description methods operands are described in the operand column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). when there are two or more description methods, select one of them. alphabetic letters in capitals and the symbols, #, !, $, and [ ], are keywords and must be described as they are. each symbol has the following meaning. #: immediate data specification $: relative address specification !: absolute address specification [ ]: indirect address specification in the case of immediate data, describe an appropriate numeric value or a label. when using a label, be sure to describe the #,!, $, or [ ] symbols. for operand register identifiers, r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for description. table 6-1. operand identifiers and description methods identifier description method r rp sfr x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7), ax (rp0), bc (rp1), de (rp2), hl (rp3) special function register symbol saddr saddrp fe20h to ff1fh immediate data or label fe20h to ff1fh immediate data or label (even address only) addr16 addr5 0000h to ffffh immediate data or label (only even addresses for 16-bit data transfer instructions) 0040h to 007fh immediate data or label (even address only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label
21 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 6.1.2 descriptions of the operation field a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag ie: interrupt request enable flag nmis: non-maskable interrupt servicing flag ( ): memory contents indicated by address or register contents in parentheses x h , x l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive or : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 6.1.3 description of the flag operation field (blank): not affected 0: cleared to 0 1: set to 1 : set/cleared according to the result r: previously saved value is restored
22 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 6.2 operations flags mnemonic operand bytes clock operation zaccy mov r. #byte 3 6 r ? byte saddr, #byte 3 6 (saddr) ? byte sfr, #byte 3 6 sfr ? byte a, r note 1 24a ? r r, a note 1 24r ? a a, saddr 2 4 a ? (saddr) saddr, a 2 4 (saddr) ? a a, sfr 2 4 a ? sfr sfr, a 2 4 sfr ? a a, !addr16 3 8 a ? (addr16) !addr16, a 3 8 (addr16) ? a psw, #byte 3 6 psw ? byte a, psw 2 4 a ? psw psw, a 2 4 psw ? a a, [de] 1 6 a ? (de) [de], a 1 6 (de) ? a a, [hl] 1 6 a ? (hl) [hl], a 1 6 (hl) ? a a, [hl + byte] 2 6 a ? (hl + byte) [hl + byte], a 2 6 (hl + byte) ? a xch a, x 1 4 a ?? x a, r note 2 26a ?? r a, saddr 2 6 a ?? (saddr) a, sfr 2 6 a ?? (sfr) a, [de] 1 8 a ?? (de) a, [hl] 1 8 a ?? (hl) a, [hl + byte] 2 8 a ?? (hl+byte) movw rp, #word 3 6 rp ? word ax, saddrp 2 6 ax ? (saddrp) saddrp, ax 2 8 (saddrp) ? ax ax, rp note 3 1 4 ax ? rp rp, ax note 3 14rp ? ax notes 1. except r = a 2. except r = a, x 3. only when rp = bc, de, hl remark one clock of an instruction is one clock of the cpu clock (f cpu ) selected using the processor clock control register (pcc).
23 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 flags mnemonic operand bytes clock operation zaccy xchw ax, rp note 1 8 ax ?? rp add a, #byte 2 4 a, cy ? a + byte saddr, #byte 3 6 (saddr), cy ? (saddr) + byte a, r 2 4 a, cy ? a + r a, saddr 2 4 a, cy ? a + (saddr) a, !addr16 3 8 a, cy ? a + (addr16) a, [hl] 1 6 a, cy ? a + (hl) a, [hl + byte] 2 6 a, cy ? a + (hl + byte) addc a, #byte 2 4 a, cy ? a + byte + cy saddr, #byte 3 6 (saddr), cy ? (saddr) + byte + cy a, r 2 4 a, cy ? a + r + cy a, saddr 2 4 a, cy ? a+ (saddr) + cy a, !addr16 3 8 a, cy ? a+ (addr16) +cy a, [hl] 1 6 a, cy ? a + (hl) + cy a, [hl + byte] 2 6 a, cy ? a+ (hl + byte) + cy sub a, #byte 2 4 a, cy ? a C byte saddr, #byte 3 6 (saddr), cy ? (saddr) C byte a, r 2 4 a, cy ? a C r a, saddr 2 4 a, cy ? a C (saddr) a, !addr16 3 8 a, cy ? a C (addr16) a, [hl] 1 6 a, cy ? a C (hl) a, [hl + byte] 2 6 a, cy ? a C (hl + byte) subc a, #byte 2 4 a, cy ? a C byte C cy saddr, #byte 3 6 (saddr), cy ? (saddr) C byte C cy a, r 2 4 a, cy ? a C r C cy a, saddr 2 4 a, cy ? a C (saddr) C cy a, !addr16 3 8 a, cy ? a C (addr16) C cy a, [hl] 1 6 a, cy ? a C (hl) C cy a, [hl + byte] 2 6 a, cy ? a C (hl + byte) C cy note only when rp = bc, de, hl remark one clock of an instruction is one clock of the cpu clock (f cpu ) selected using the processor clock control register (pcc).
24 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 flags mnemonic operand bytes clock operation zaccy and a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) a, [hl + byte] 2 6 a ? a (hl + byte) or a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) a, [hl + byte] 2 6 a ? a (hl + byte) xor a, #byte 2 4 a ? a byte saddr, #byte 3 6 (saddr) ? (saddr) byte a, r 2 4 a ? a r a, saddr 2 4 a ? a (saddr) a, !addr16 3 8 a ? a (addr16) a, [hl] 1 6 a ? a (hl) a, [hl + byte] 2 6 a ? a (hl + byte) cmp a, #byte 2 4 a C byte saddr, #byte 3 6 (saddr) C byte a, r 2 4 a C r a, saddr 2 4 a C (saddr) a, !addr16 3 8 a C (addr16) a, [hl] 1 6 a C (hl) a, [hl + byte] 2 6 a C (hl + byte) addw ax, #word 3 6 ax, cy ? ax + word subw ax, #word 3 6 ax, cy ? ax C word cmpw ax, #word 3 6 ax C word inc r 2 4 r ? r + 1 saddr 2 4 (saddr) ? (saddr) + 1 dec r 2 4 r ? rC 1 saddr 2 4 (saddr) ? (saddr) C 1 remark one clock of an instruction is one clock of the cpu clock (f cpu ) selected using the processor clock control register (pcc).
25 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 flags mnemonic operand bytes clock operation zaccy incw rp 1 4 rp ? rp + 1 decw rp 1 4 rp ? rp C 1 ror a, 1 1 2 (cy, a 7 ? a 0 , a m-1 ? a m ) 1 rol a, 1 1 2 (cy, a 0 ? a 7 , a m+1 ? a m ) 1 rorc a, 1 1 2 (cy ? a 0 , a 7 ? cy, a m-1 ? a m ) 1 rolc a, 1 1 2 (cy ? a 7 , a 0 ? cy, a m+1 ? a m ) 1 set1 saddr.bit 3 6 (saddr.bit) ? 1 sfr.bit 3 6 sfr.bit ? 1 a.bit 2 4 a.bit ? 1 psw.bit 3 6 psw.bit ? 1 [hl].bit 2 10 (hl).bit ? 1 clr1 saddr.bit 3 6 (saddr.bit) ? 0 sfr.bit 3 6 sfr.bit ? 0 a.bit 2 4 a.bit ? 0 psw.bit 3 6 psw.bit ? 0 [hl].bit 2 10 (hl).bit ? 0 set1 cy 1 2 cy ? 11 clr1 cy 1 2 cy ? 00 not1 cy 1 2 cy ? cy call !addr16 3 6 (sp C 1) ? (pc + 3) h , (sp C 2) ? (pc + 3) l , pc ? addr16, sp ? sp C 2 callt [addr5] 1 8 (sp C 1) ? (pc + 1) h , (sp C 2) ? (pc + 1) l , pc h ? (00000000, addr5 + 1) pc l ? (00000000, addr5) sp ? sp C 2 ret 1 6 pc h ? (sp + 1), pc l ? (sp), sp ? sp + 2 reti 1 8 pc h ? (sp + 1), pc l ? (sp), psw ? (sp + 2), sp ? sp + 3, nmis ? 0 rrr push psw 1 2 (sp C 1) ? psw, sp ? sp C 1 rp 1 4 (sp C 1) ? rp h , (sp C 2) ? rp l , sp ? sp -C 2 pop psw 1 4 psw ? (sp), sp ? sp + 1 r r r rp 1 6 rp h ? (sp + 1), rp l ? (sp), sp ? sp + 2 movw sp, ax 2 8 sp ? ax ax, sp 2 6 ax ? sp remark one clock of an instruction is one clock of the cpu clock (f cpu ) selected using the processor clock control register (pcc).
26 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 flags mnemonic operand bytes clock operation zaccy br !addr16 3 6 pc ? addr16 $addr16 2 6 pc ? pc + 2 + jdisp8 ax 1 6 pc h ? a, pc l ? x bc $addr16 2 6 pc ? pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 pc ? pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 pc ? pc + 2 + jdisp8 if z = 1 bnz $addr16 2 6 pc ? pc + 2 + jdisp8 if z = 0 bt saddr.bit, $saddr16 4 10 pc ? pc + 4 + jdisp8 if (saddr. bit) = 1 sfr.bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if sfr. bit = 1 a.bit, $saddr16 3 8 pc ? pc + 3 + jdisp8 if a. bit = 1 psw.bit $addr16 4 10 pc ? pc + 4 + jdisp8 if psw. bit = 1 bf saddr.bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if (saddr. bit) = 0 sfr.bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if sfr. bit = 0 a.bit, $addr16 3 8 pc ? pc + 3 + jdisp8 if a. bit = 0 psw.bit, $addr16 4 10 pc ? pc + 4 + jdisp8 if psw. bit = 0 dbnz b, $addr16 2 6 b ? b C 1, then pc ? pc + 2 + jdisp8 if b 1 0 c, $addr16 2 6 c ? c C 1, then pc ? pc + 2 + jdisp8 if c 1 0 saddr, $addr16 3 8 (saddr) ? (saddr) C 1, then pc ? pc + 3 + jdisp8 if (saddr) 1 0 nop 1 2 no operation ei 3 6 ie ? 1 (enable interrupt) di 3 6 ie ? 0 (disable interrupt) halt 1 2 set halt mode stop 1 2 set stop mode remark one clock of an instruction is one clock of the cpu clock (f cpu ) selected using the processor clock control register (pcc).
27 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 7. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd v av dd v av ref av dd - 0.3 v v dd av dd + 0.3 v av ref av dd + 0.3 v av ref v dd + 0.3 v - 0.3 to +6.5 v supply voltage v pp - 0.3 to +10.5 v v i1 pins other than p50 to p53, p23, p24 - 0.3 to v dd + 0.3 v v i2 p23, p24 - 0.3 to +5.5 v input voltage v i3 p50 to p53 - 0.3 to +13 v output voltage v o - 0.3 to v dd + 0.3 v per pin - 10 ma output current, high i oh total for all pins - 30 ma per pin 30 ma output current, low i ol total for all pins 160 ma in normal operation mode - 40 to +85 c operating ambient temperature t a during flash memory programming +10 to +40 c storage temperature t stg - 40 to +125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
28 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 main system clock oscillator characteristics (t a = - - - - 40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) note 1 v dd = oscillation voltage range 1.0 5.0 mhz ceramic resonator x2 x1 v pp c2 c1 oscillation stabilization time note 2 after v dd reaches oscillation voltage range min. 4ms oscillation frequency (f x ) note 1 1.0 5.0 mhz v dd = 4.5 to 5.5 v 10 crystal resonator x2 x1 v pp c2 c1 oscillation stabilization time note 2 30 ms x1 input frequency (f x ) note 1 1.0 5.0 mhz x1 input high-/low-level width (t xh , t xl ) 85 500 ns x1 input frequency (f x ) note 1 v dd = 2.7 to 5.5 v 1.0 5.0 mhz external clock x1 input high-/low-level width (t xh , t xl ) v dd = 2.7 to 5.5 v 85 500 ns notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. use a resonator that stabilizes oscillation within the oscillation wait time. cautions 1. when using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss0 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. when the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. x1 x2 x1 x2 open
29 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 subsystem clock oscillator characteristics (t a = - - - - 40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz v dd = 4.5 to 5.5 v 1.2 2 s crystal resonator xt2 xt1 v pp c4 c3 r oscillation stabilization time note 2 10 s xt1 input frequency (f xt ) note 1 32 35 khz external clock xt1 input high-/low-level width (t xth , t xtl ) 14.3 15.6 m s notes 1. indicates only oscillator characteristics. refer ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss0 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. xt1 xt2
30 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 dc characteristics (t a = - - - - 40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit per pin - 1ma output current , high i oh total for all pins - 15 ma per pin 10 ma output current, low i ol total for all pins 80 ma v dd = 2.7 to 5.5 v 0.7 v dd v dd v v ih1 p00 to p05, p10, p11,p60 to p67 0.9 v dd v dd v v dd = 2.7 to 5.5 v 0.7 v dd 12 v v ih2 p50 to p53 v dd = 1.8 to 5.5 v, t a = 25 to +85 c 0.9 v dd 12 v v dd = 2.7 to 5.5 v 0.8 v dd v dd v v ih3 reset, p20 to p26, p30 to p33 0.9 v dd v dd v v dd = 4.5 to 5.5 v v dd - 0.5 v dd v input voltage, high v ih4 x1, x2, xt1, xt2 v dd - 0.1 v dd v v dd = 2.7 to 5.5 v 0 0.3 v dd v v il1 p00 to p05, p10, p11, p60 to p67 0 0.1 v dd v v dd = 2.7 to 5.5 v 0 0.3 v dd v v il2 p50 to p53 0 0.1 v dd v v dd = 2.7 to 5.5 v 0 0.2 v dd v v il3 reset,p20 to p26, p30 to p33 0 0.1 v dd v v dd = 4.5 to 5.5 v 0 0.4 v input voltage, low v il4 x1, x2, xt1, xt2 00.1v v dd = 4.5 to 5.5 v, i oh = - 1 ma v dd - 1.0 v output voltage, high v oh pins other than p23, p24, p50 to p53 v dd = 1.8 to 5.5 v, i oh = - 100 m av dd - 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma 1.0 v v ol1 pins other than p50 to p53 v dd = 1.8 to 5.5 v, i ol = 400 m a0.5v v dd = 4.5 to 5.5 v, i ol = 10 ma 1.0 v output voltage, low v ol2 p50 to p53 v dd = 1.8 to 5.5 v, i ol = 1.6 ma 0.4 v i lih1 pins other than p50 to p53 (n-ch open-drain) x1, x2, xt1, and xt2 3 m a i lih2 v i = v dd x1, x2, xt1, xt2 20 m a input leakage current, high i lih3 v i = 12 v p50 to p53 (n-ch open drain) 20 m a i lil1 pins other than p50 to p53 (n-ch open-drain) x1, x2, xt1, and xt2 - 3 m a i lil2 x1, x2, xt1, xt2 - 20 m a input leakage current, low i lil3 v i = 0 v p50 to p53 (n-ch open drain) - 3 note m a output leakage current, high i loh v o = v dd 3 m a output leakage current, low i lol v o = 0 v - 3 m a software pull-up resistor r 1 v i = 0 v, for pins other than p23, p24, and p50 to p53 50 100 200 k w note a low-level input leakage current of -60 m a(max.) flows only during the 1-cycle time after a read instruction is executed to p50 to p53 and p50 to p53 are set to input mode. at times other than this, -3 m a (max.) current flows. remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
31 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 dc characteristics (t a = - - - - 40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 10% note 4 5.0 15.0 ma v dd = 3.0 v 10% note 5 2.0 5.0 ma i dd1 note 1 5.0-mhz crystal oscillation operating mode (c1 = c2 = 22pf) v dd = 2.0 v 10% note 5 1.5 3.0 ma v dd = 5.0 v 10% note 4 2.0 6.0 ma v dd = 3.0 v 10% note 5 1.0 2.5 ma i dd2 note 1 5.0-mhz crystal oscillation halt mode (c1 = c2 = 22pf) v dd = 2.0 v 10% note 5 0.75 1.5 ma v dd = 5.0 v 10% 250 750 m a v dd = 3.0 v 10% 200 600 m a i dd3 note 1 32.768-khz crystal oscillation operating mode note 3 (c3 = c4 = 22pf, r = 220k w ) v dd = 2.0 v 10% 150 450 m a v dd = 5.0 v 10% 50 150 m a v dd = 3.0 v 10% 30 90 m a i dd4 note 1 32.768-khz crystal oscillation halt mode note 3 (c3 = c4 = 22pf, r = 220k w ) v dd = 2.0 v 10% 20 60 m a v dd = 5.0 v 10% 0.1 30 m a v dd = 3.0 v 10% 0.05 10 m a i dd5 note 1 32.768-khz crystal stop stop mode v dd = 2.0 v 10% 0.05 10 m a v dd = 5.0 v 10% note 4 6.0 17.0 ma v dd = 3.0 v 10% note 5 3.0 7.0 ma power supply current i dd6 note 2 5.0-mhz crystal oscillation a/d operating mode (c1 = c2 = 22pf) v dd = 2.0 v 10% note 5 2.5 5.0 ma notes 1. the av ref on (adcs0 (bit 7 of adm0; a/d converter mode register 0) = 1), av dd , and the port current (including the current flowing through the internal pull-up resistors) are not included. 2. the av ref on (adcs0 =1) and port current (including the current flowing through the internal pull-up resistors) are not included. refer to the a/d converter characteristics for the current flowing through av ref . 3. when the main system clock is stopped. 4. during high-speed mode operation (when the processor clock control register (pcc) is set to 00h.) 5. during low-speed mode operation (when pcc is set to 02h) remark unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
32 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 ac characteristics (1) basic operation (t a = - - - - 40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 0.4 8 m s operation based on the main system clock 1.6 8 m s cycle time (minimum instruction execution time) t cy operation based on the subsystem clock 114 122 125 m s v dd = 2.7 to 5.5 v 0 4 mhz ti80 and ti81 input frequency f ti 0 275 khz v dd = 2.7 to 5.5 v 0.1 m s ti80 and ti81 input high-/low-level width t tih , t til 1.8 m s interrupt input high- /low-level width t inth , t intl intp0 to intp3 10 m s reset input low- level width t rsl 10 m s cpt90 input high- /low-level width t cph , t cpl 10 m s t cy vs v dd (main system clock) supply voltage v dd [v] 123456 0.1 0.4 0.5 1.0 2.0 10 60 cycle time t cy [ s] guaranteed operation range m
33 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 (2) serial interface (t a = - - - - 40 to +85 c, v dd = 1.8 to 5.5 v) (a) 3-wire serial i/o mode (sck20...internal clock) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy1 3200 ns v dd = 2.7 to 5.5 v t kcy1 /2 - 50 ns sck20 high-/low- level width t kh1 , t kl1 t kcy1 /2 - 150 ns v dd = 2.7 to 5.5 v 150 ns si20 setup time (to sck20 - ) t sik1 500 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 - ) t ksi1 600 ns v dd = 2.7 to 5.5 v 0 250 ns so20 output delay time from sck20 t kso1 r = 1 k w , c = 100 pf note 0 1000 ns note r and c are the load resistance and load capacitance of the so20 output line. (b) 3-wire serial i/o mode (sck20...external clock) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 900 ns sck20 cycle time t kcy2 3500 ns v dd = 2.7 to 5.5 v 400 ns sck20 high-/low- level width t kh2 , t kl2 1600 ns v dd = 2.7 to 5.5 v 100 ns si20 setup time (to sck20 - ) t sik2 150 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 - ) t ksi2 600 ns v dd = 2.7 to 5.5 v 0 300 ns so20 output delay time from sck20 t kso2 r = 1 k w , c = 100 pf note 0 1000 ns v dd = 2.7 to 5.5 v 120 ns so20 setup time (when using ss20, to ss20 ) t kas2 400 ns v dd = 2.7 to 5.5 v 240 ns so20 disable time (when using ss20, from ss20 - ) t kds2 800 ns note r and c are the load resistance and load capacitance of the so20 output line. (c) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 78125 bps transfer rate 19531 bps
34 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 (d) uart mode (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 900 ns asck20 cycle time t kcy3 3500 ns v dd = 2.7 to 5.5 v 400 ns asck20 high-/low- level width t kh3 , t kl3 1600 ns v dd = 2.7 to 5.5 v 39063 bps transfer rate 9766 bps asck20 rise time, fall time t r , t f 1 m s
35 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 (3) serial interface smb0 (t a = - - - - 40 to +85 c, v dd = 1.8 to 5.5 v) ( m m m m pd78f9177y only) (a) dc characteristics parameter symbol conditions min. typ. max. unit input voltage, high v ih scl0, sda0 (at hysteresis) 0.8 v dd v dd v input voltage, low v il scl0, sda0 (at hysteresis) 0 0.2 v dd v v dd = 4.5 to 5.5 v, i ol = 10 ma 1.0 v output voltage, high v ol scl0, sda0 v dd = 1.8 to 5.5 v, i ol = 400 m a0.5 v input leakage current, high i lih scl0, sda0 v i = v dd 3 m a input leakage current, low i lil scl0, sda0 v i = 0 v - 3 m a (b) dc characteristics (when using comparator) parameter symbol conditions min. typ. max. unit input range v sda , v scl v dd = 1.8 to 5.5 v 0 5.5 v 4.5 v dd 5.5 v 0.72 v ismb v ismb 1.28 v ismb v 3.3 v dd < 4.5 v 0.78 v ismb v ismb 1.22 v ismb v 2.7 v dd < 3.3 v 0.75 v ismb v ismb 1.25 v ismb v transfer level v isda , v iscl 1.8 v dd < 2.7 v 0.90 v ismb v ismb 1.45 v ismb v lvl01, lvl00 = 0, 1 0.25 v dd v lvl01, lvl00 = 1, 0 0. 375 v dd v input level threshold value v ismb lvl01, lvl00 = 1, 1 0.5 v dd v note v ismb is an input level threshold value selected by bits lvl00 and lvl01 (bits 0 and 1 of smb input level setting register 0 (smbvi0)). according to the smb standard (v1.1), the maximum value of low-level input voltage is 0.8 v, and the minimum value of high-level input voltage, 2.1 v. to satisfy these conditions, set lvl01 and lvl00 as follows; when v dd = 1.8 to 3.3 v: lvl01, lvl00 = 1, 1 (0.5 v dd ) when v dd = 3.3 to 4.5 v: lvl01, lvl00 = 1, 0 (0.375 v dd ) when v dd = 4.5 to 5.5 v: lvl01, lvl00 = 0, 1 (0.25 v dd ) "lvl01, lvl00 = 0, 0" is not available since this setting does not satisfy the smb standard (v1.1).
36 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 (c) ac characteristics smb mode standard mode i 2 c bus high-speed mode i 2 c bus parameter symbol min. max. min. max. min. max. unit scl0 clock frequency f clk 10 100 0 100 0 400 khz bus free time (between stop and start condition) t buf 4.7 - 4.7 - 1.3 - m s hold time note1 t hd:sta 4.0 - 4.0 - 0.6 - m s start/restart condition setup time t su:sta 4.7 - 4.7 - 0.6 - m s stop condition setup time t su:sto 4.0 - 4.0 - 0.6 - m s when using cbus- compatible master -- 5 --- m s data hold time when using smb/iic bus t hd:dat 300 --- 0 note2 900 note3 ns data setup time t su:dat 250 - 250 - 100 note4 - ns scl0 clock low-level width t low 4.7 - 4.7 - 1.3 - m s scl0 clock high-level width t high 4.0 50 4.0 - 0.6 - m s scl0 and sda0 signal fall time t f - 300 - 300 - 300 ns scl0 and sda0 signal rise time t r - 1000 - 1000 - 300 ns spike pulse width controlled by input filter t sp ---- 050ns timeout t timeout 25 35 -- - - ms total extended time of scl0 clock low-level period (slave) t low:sext - 25 -- - - ms total extended time of cumulative clock low-level period (master) t low:mext - 10 -- - - ms capacitive load per each bus line cb --- 400 - 400 pf notes 1. in the start condition, the first clock pulse is generated after this hold time. 2. to fill in the underfined area of the scl0 falling edge, it is necessary for the device to internally provide at least 300 ns of hold time for the sda0 signal (which is v ihmin . of the scl0 signal). 3. if the device does not extend the scl0 signal low hold time (t low ), only maximum data hold time t hd:dat needs to be fulfilled. 4. the high-speed mode i 2 c bus is available in the smb mode and the standard mode i 2 c bus system. at this time, the conditions described below must be satisfied. if the device extends the scl0 signal low state hold time t su:dat 3 250 ns if the device extends the scl0 signal low state hold time be sure to transmit the next data bit to the sda0 line before the scl0 line is released (t rmax. + t su:dat = 1000 + 250 = 1250 ns by the smb mode or the standard mode i 2 c bus specification).
37 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 ac timing measurement points (excluding the x1 and xt1 inputs) clock timing ti timing 0.8 v dd 0.2 v dd point of measurement 0.8 v dd 0.2 v dd 1/f x t xl t xh x1 input v ih4 (min.) v il4 (max.) 1/f xt t xtl t xth xt1 input v ih4 (min.) v il4 (max.) 1/f ti t til t tih ti80, ti81
38 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 interrupt input timing intp0-intp3 t intl t inth reset input timing reset t rsl cpt90 input timing cpt90 t cpl t cph
39 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 serial transfer timing 3-wire serial i/o mode: remark m = 1, 2 3-wire serial i/o mode (when using ss20): uart mode (external clock input): sck20 t klm t kcym t khm si20 input data t ksim t sikm output data t ksom so20 asck20 t r t f t kl3 t kcy3 t kh3 t kas2 so20 ss20 output data t kds2
40 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 smb mode: t r t low t f t high t hd:sta stop condition start condition restart condition stop condition t buf t su:dat t su:sta t hd:sta t sp t su:sto t hd:dat scl0 sda0
41 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 10-bit a/d converter characteristics (t a = - - - - 40 to +85 c, 1.8 av ref av dd = v dd 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit 4.5 v av ref av dd 5.5 v 0.2 0.4 %fsr 2.7 v av ref av dd 5.5 v 0.4 0.6 %fsr overall error note 1.8 v av ref av dd 5.5 v 0.8 1.2 %fsr 4.5 v av ref av dd 5.5 v 14 100 m s 2.7 v av ref av dd 5.5 v 14 100 m s conversion time t conv 1.8 v av ref av dd 5.5 v 28 100 m s 4.5 v av ref av dd 5.5 v 0.4 %fsr 2.7 v av ref av dd 5.5 v 0.6 %fsr zero-scale error note 1.8 v av ref av dd 5.5 v 1.2 %fsr 4.5 v av ref av dd 5.5 v 0.4 %fsr 2.7 v av ref av dd 5.5 v 0.6 %fsr full-scale error note 1.8 v av ref av dd 5.5 v 1.2 %fsr 4.5 v av ref av dd 5.5 v 2.5 lsb 2.7 v av ref av dd 5.5 v 4.5 lsb integral linearity error note inl 1.8 v av ref av dd 5.5 v 8.5 lsb 4.5 v av ref av dd 5.5 v 1.5 lsb 2.7 v av ref av dd 5.5 v 2.0 lsb differential linearity error note dnl 1.8 v av ref av dd 5.5 v 3.5 lsb analog input voltage v ian 0av ref v reference voltage av ref 1.8 av dd v resistance between av ref and av ss r airef 20 40 k w note excludes quantization error ( 0.05%fsr). remark fsr: full scale range
42 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 flash memory write/delete characteristics (t a = 10 to 40 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit write current (v dd pin) note i ddw when v pp supply voltage = v pp1 (5.0-mhz crystal oscillation operation mode) 18 ma write current (v pp pin) note i ppw when v pp supply voltage = v pp1 7.5 ma delete current (v dd pin) note i dde when v pp supply voltage = v pp1 (5.0-mhz crystal oscillation operation mode) 18 ma delete current (v pp pin) note i ppe when v pp supply voltage = v pp1 100 ma unit delete time t er 0.5 1 1 s total delete time t era 20 s write count delete/write are regarded as 1 cycle 20 times v pp0 in normal operation 0 0.2v dd v v pp supply voltage v pp1 during flash memory programming 9.7 10.0 10.3 v note the current flowing to the ports (including the current flowing through an on-chip pull-up resistor) and av dd current are not included. data memory stop mode low power supply voltage data retention characteristics (t a = - - - - 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention power supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 m s release by reset 2 15 /f x s oscillation stabilization wait time note 1 t wait release by interrupt request note 2 s notes 1. the oscillation stabilization time is the time the cpu operation is stopped to prevent unstable operation when oscillation starts. 2. by using bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time selection register (osts), 2 12 /f x , 2 15 /f x , or 2 17 /f x can be selected. remark f x : main system clock oscillation frequency
43 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 data retention timing (stop mode release by reset) v dd data retention mode stop mode halt mode internal reset operation operating mode t srel t wait stop instruction execution v dddr reset data retention timing (standby release signal: stop mode release by interrupt signal) v dd data retention mode stop mode halt mode operating mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
44 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 8. characteristics curves 10.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 01234 supply voltage v dd (v) 5678 x1 x2 22 pf xt1 xt2 33 pf 220 k w v ss 22 pf 33 pf v ss supply current i dd (ma) crystal resonator 5.0 mhz crystal resonator 32.768 khz subsystem clock operation halt mode (css0 = 1, mcc = 1) subsystem clock operating mode (css0 = 1, mcc = 1) main system clock operation halt mode (pcc1 = 1, css0 = 0) main system clock operation halt mode (pcc1 = 1, css0 = 0) main system clock operating mode (pcc1 = 1, css0 = 0) main system clock operating mode (pcc1 = 0, css0 = 0) (t a = 25 ?c)
45 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 9. package drawing 33 34 22 44 1 12 11 23 44 pin plastic qfp (10x10) item millimeters n q 0.1 0.05 0.10 u 0.6 0.15 s44gb-80-8es-1 j i h n a 12.0 0.2 b 10.0 0.2 c 10.0 0.2 d 12.0 0.2 f g h 1.0 0.37 1.0 i j k 0.8 (t.p.) 1.0 0.2 0.2 l 0.5 m 0.17 s 1.6 max. r3 ? + 0.08 - 0.07 + 0.03 - 0.06 + 4 ? - 3 ? detail of lead end f g k m m p 1.4 0.05 note each lead centerline is located within 0.16 mm of its true position (t.p.) at maximum material condition. s s a b cd u r s p q l t
46 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. a s p b cd m g h k i j r detail of lead end f 48-pin plastic tqfp (fine pitch) (7x7) item millimeters a 9.0 0.2 b 7.0 0.2 f 0.75 g h 0.75 c 7.0 0.2 d 9.0 0.2 p48ga-50-9eu i 0.10 l 0.5 0.2 j 0.5 (t.p.) k 1.0 0.2 m 36 37 24 48 1 13 12 25 s n s q l t u 0.22 + 0.05 - 0.04 m n 0.08 p 1.0 0.1 q 0.1 0.05 0.17 + 0.03 - 0.07 r s 1.27 max. 3 ? + 4 ? - 3 ?
47 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 10. recommended soldering conditions the m pd78f9177 and m pd789177y should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e ). for soldering methods and conditions other than those recommended below, contact your nec sales representative. table 10-1. surface mounting type soldering conditions (1/2) m m m m pd78f9177gb-8es: 44-pin plastic lqfp (10 10) m m m m pd78f9177ygb-8es: 44-pin plastic lqfp (10 10) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: twice or less ir35-00-2 vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: twice or less vp15-00-2 wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, preheating temperature: 120 c max. (package surface temperature) ws60-00-1 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) - caution do not use different soldering methods together (except for partial heating). table 10-1. surface mounting type soldering conditions (2/2) m m m m pd78f9177yga-9eu: 48-pin plastic tqfp (7 7) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: twice or less, number of days:3 note (after that, prebaking sis necessary at 125 c for 10 hours) ir35-103-2 vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: twice or less, number of days:3 note (after that, prebaking sis necessary at 125 c for 10 hours) vp15-103-2 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) - note the number of days for storage at 25 c, 65% rh max after the dry pack has been opened. caution do not use different soldering methods together (except for partial heating).
48 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 appendix a. differences between m pd78f9177, 78f9177y, and mask rom versions the m pd78f9177 and m pd78f9177y are flash memory version of the mask rom version. the differences between the m pd78f9177, 78f9177y and the mask rom versions are shown in table a-1. table a-1. differences between m m m m pd78f9177, 78f9177y and mask rom versions flash memory version mask rom version product name item m pd78f9177, 78f9177y m pd789166, 789166y 789176, 789176y m pd789167, 789167y 789177, 789177y rom 24 kb 16 kb 24 kb internal memory high-speed ram 512 bytes v pp pin provided not provided pull-up resistor 17 (software control) 21 (software control: 17, mask option specification: 4) a/d resolution 10 bits 8 bits ( m pd789166, 789167, 789166y, 789167y) 10 bits ( m pd789176, 789177, 789176y, 789177y) electrical specifications see the relevant data sheet cautions 1. there are differences in the amount of noise immunity and noise radiation between the flash memory and mask rom versions. when pre-producing an application set with the flash memory version and then mass producing it with the mask rom versions, be sure to conduct sufficient evaluations on the commercial samples (cs) (not engineering sample, es) of the mask rom version. 2. when the m m m m pd78f9177, a flash memory counterpart of the m m m m pd789166 or m m m m pd789167, is used, however, adcr0 can be manipulated with an 8-bit memory manipulation instruction. in this case, use an object file assembled with the m m m m pd789166 or m m m m pd789167. the same is also true for the m m m m pd78f9177y, a flash memory counterpart of the m m m m pd789166y or m m m m pd789167y. when the m m m m pd78f9177y is used, adcr0 can be manipulated with an 8-bit memory manipulation instruction. in this case, use an object file assembled with the m m m m pd789166y or m m m m pd789167y.
49 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 appendix b. development tools the following development tools are available for developing systems using the m pd78f9177 and m pd78f9177y. language processing software ra78k0s notes 1, 2, 3 assembler package common to 78k/0s series cc78k0s notes 1, 2, 3 c compiler package common to 78k/0s series df789177 notes 1, 2, 3 device file for m pd789167, 789177, 789167y, and 789177y subseries cc78k0s-l notes 1, 2, 3 c compiler library source file common to 78k/0s series flash memory writing tools flashpro lil (part no. fl-pr3 note 4 , pg-fp3) flash programmer dedicated for on-chip flash memory microcontrollers fa-44gb-8es note 4 flash memory programming adapter for 44-pin plastic lqfp (gb-8es type) fa-48ga flash memory programming adapter for 48-pin plastic tqfp (fine pitch) (ga-9eu type) debugging tools(1/2) ie-78k0s-ns in-circuit emulator in-circuit emulator used to debug hardware or software when application systems which use the 78k/0s series are developed. the ie-78k0s-ns supports an integrated debugger (id78k0s-ns). the ie-78k0s-ns is used in combination with an interface adapter for connection to an ac adapter, emulation probe, or host machine. ie-70000-mc-ps-b ac adapter adapter used to supply power from a 100- to 240-v ac outlet ie-70000-98-if-c interface adapter adapter required when using the pc-9800 series (excluding notebook pcs) as the host machine for the ie-78k0s-ns (c bus supported) ie-70000-cd-if-a pc card/interface pc card and interface cable required when using a notebook pc as the host machine for the ie-78k0s-ns (pcmcia socket supported) ie-70000-pc-if-c interface adapter adapter required when using an ibm pc/at tm or compatible as the host machine for the ie-78k0s-ns (isa bus supported) ie-70000-pci-if interface adapter adapter required when using a pc equipped with a pci bus as the host machine for the ie-78k0s-ns ie-789177-ns-em1 emulation board emulation board used to emulate the peripheral hardware specific to the device. this is used in combination with the in-circuit emulator. board to connect an in-circuit emulator to the target system. this is used in combination with the ev-9200g-44 np-44gb note 4 emulation probe ev-9200g-44 conversion socket conversion socket to connect the target system board on which a 44-pin plastic lqfp can be mounted and the np-44gb board to connect an in-circuit emulator to the target system. this is used in combination with the tgb-044sap. np-44gb-tq note 4 emulation probe tgb-044sap note 5 conversion socket conversion socket to connect the target system board on which a 44-pin plastic lqfp can be mounted and the np-44gb-tq
50 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 debugging tools(2/2) board to connect an in-circuit emulator to the target system. this is used in combination with the tga-048sdp. np-48ga note 4 emulation probe tga-048sdp note 5 conversion socket conversion socket to connect the target system board on which a 48-pin plastic tqfp (fine pitch) can be mounted and the np-48ga sm78k0s notes 1, 2 system simulator common to 78k/0s series id78k0s-ns notes 1, 2 integrated debugger common to 78k/0s series df789177 notes 1, 2 device file for m pd789167, 789177, 789167, and 789177y subseries real-time os mx78k0s notes 1, 2 os for 78k/0s series notes 1. based on the pc-9800 series (japanese windows tm ) 2. based on ibm pc/at and compatibles (japanese windows/english windows) 3. based on the hp9000 series 700 tm (hp-ux tm ), sparcstation tm (sunos tm , soraris tm ), and news tm (news-os tm ) 4. product made by and available from naito densei machida mfg. co., ltd. (+81-44-822-3813). 5. product made by tokyo eletech corporation. refer to: daimaru kogyo, ltd. tokyo electronic division (+81-3-3820-7112) osaka electronic division (+81-6-6244-6672) remark the ra78k0s, cc78k0s, and sm78k0s can be used in combination with the df789177.
51 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 appendix c. related documents documents related to devices document no. document name japanese english m pd789166, 167, 176, 177, 166y, 167y, 176y, 177y, 166(a), 167(a), 176(a), 177(a), 166y(a), 167y(a), 176y(a), 177y(a) data sheet u14017j u14017e m pd78f9177, 78f9177y data sheet u14022j this manual m pd789167, 789177, 789167y, 789177y subseries users manual u14186j u14186e 78k/0s series instruction users manual u11047j u11047e document related to development tools (users manuals) document no. document name japanese english operation u11622j u11622e assembly language u11599j u11599e ra78k0s assembler package structured assembly language u11623j u11623e operation u11816j u11816e cc78k0s c compiler language u11817j u11817e sm78k0s system simulator windows based reference u11489j u11489e sm78k series system simulator external parts user open interface specifications u10092j u10092e id78k0s-ns windows based reference u12901j u12901e ie-78k0s-ns in-circuit emulator u13549j u13549e ie-789177-ns-em1 emulation board u14621j u14621e documents related to embedded software (users manuals) document no. document name japanese english os for 78k/0s series mx78k0s fundamental u12938j u12938e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
52 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 other documents document no. document name japanese english semiconductor selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor device c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892j c11892e guide to microcomputer-related products by third party u11416j - caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing. the related document indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such.
53 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 [memo]
54 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 eeprom is a trademark of nec corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. news and news-os are trademarks of sony corporation. notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
55 m m m m pd78f9177, 78f9177y data sheet u14022ej1v0ds00 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. madrid office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp brasil tel: 55-11-6462-6810 fax: 55-11-6462-6829 j00.7
m m m m pd78f9177, 78f9177y m8e 00. 4 the information in this document is current as of august, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above).

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